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March 2002
(R)
AS7C33128PFS32A AS7C33128PFS36A
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
Organization: 131,072 words x 32 or 36 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns Fully synchronous register-to-register operation Single register "Flow-through" mode Single-cycle deselect Dual-cycle deselect also available (AS7C33128PFD32A/ AS7C33128PFD36A) * Pentium(R)1 compatible architecture and timing * Asynchronous output enable control * * * * * * * * * * * * * * * Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.3 core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power in power down mode NTDTM1 pipeline architecture available (AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium(R) is a registered trademark of Intel Corporation. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
Logic block diagram
LBO CLK ADV ADSC ADSP A[16:0] 17 CLK CE CLR D Address CE register CLK D Q0 Burst logic Q1 17 Q
Pin arrangement
A6 A7 CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 128K x 32/36 Memory array 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
15
17
GWE BWE BWd
DQd Q Byte write registers CLK DQc Q Byte write registers CLK D DQb Q Byte write registers CLK DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q D D
36/32
36/32
BWc
BWb
BWa CE0 CE1 CE2
4
ZZ
OE FT
36/32 DQ [a:d]
Selection guide
-200 Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3 570 160 30 -183 5.4 183 3.1 540 140 30 -166 6 166 3.5 475 130 30 -133 7.5 133 4 425 100 30 -100 10 100 5 325 90 30 Units ns MHz ns mA mA mA
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Alliance Semiconductor
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OE Output registers CLK
Input registers CLK
DQPc/NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd/NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TQFP 14 x 20 mm
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb/NC DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa/NC
Note: Pins 1,30,51,80 are NC for x32
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Copyright (c) Alliance Semiconductor. All rights reserved.
AS7C33128PFS32A AS7C33128PFS36A
(R)
Functional description
The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology. Timing for these devices is compatible with existing Pentium(R) synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPCTM1-based systems in computing, datacom, instrumentation, and telecommunications systems. Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (tCD) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium(R) count sequence. With LBO driven LOW, the device uses a linear count sequence suitable for PowerPCTM and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/ 36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). * Master chip enable CE0 blocks ADSP, but not ADSC. AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 x 20 mm TQFP package.
Capacitance
Parameter Input capacitance I/O capacitance GWE L H H H Symbol CIN CI/O Signals Address and control pins I/O pins BWE X L H L BWn X L X H Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 WEn T T F* F* Unit pF pF
Write enable truth table (per byte)
.H\ X = Don't Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
Burst Order
Starting Address First increment Second increment Third increment Interleaved Burst Order LBO=1 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Starting Address First increment Second increment Third increment Linear Burst Order LBO=0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
1 PowerPCTM is a trademark International Business Machines Corporation.
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AS7C33128PFS32A AS7C33128PFS36A
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Signal descriptions
Signal CLK A0-A16 DQ[a,b,c,d] CE0 CE1, CE2 ADSP ADSC ADV GWE BWE BW[a,b,c,d] OE LBO FT ZZ I/O I I I/O I I I I I I I I I I I I Properties CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC default = HIGH STATIC ASYNC Description Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. Address strobe controller. Asserted LOW to load a new address or to enter standby mode. Advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a:d] are inactive the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Count mode. When driven High, count sequence follows Intel XOR convention. When driven Low, count sequence follows linear convention. This signal is internally pulled High.18 Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min -0.5 -0.5 -0.5 - - -65 -65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 50 +150 +135 Unit V V V W mA
oC o
C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Synchronous truth table
CE0 H L L L L L L L L X X X X H H H H L X H X H CE1 X L L X X H H H H X X X X X X X X H X X X X CE2 X X X H H L L L L X X X X X X X X L X X X X ADSP X L H L H L L H H H H H H X X X X H H X H X ADSC L X L X L X X L L H H H H H H H H L H H H H ADV X X X X X X X X X L L H H L L H H X L L H H
WEn1
OE X X X X X L H L H L H L H L H L H X X X X X
Address accessed NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current
CLK L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H
Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Cont. read Cont. read Suspend read Suspend read Cont. read Cont. read Suspend read Suspend read Begin write Cont. write Cont. write Suspend write Suspend write
DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z2 Hi-Z Hi-Z2 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D
X X X X X X X F F F F F F F F F F T T T T T
2 Q in flow through mode. 3For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time. Key: X = Don't Care, L = Low, H = High.
1See "Write enable truth table" on page 2 for more information.
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Recommended operating conditions
Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage Address and control pins I/O pins Ambient operating temperature Symbol VDD VSS VDDQ VSSQ VDDQ VSSQ VIH VIL VIH VIL TA Min 3.135 0.0 3.135 0.0 2.35 0.0 2.0 -0.52 2.0 -0.52 0 Nominal 3.3 0.0 3.3 0.0 2.5 0.0 - - - - - Max 3.6 0.0 3.6 0.0 2.9 0.0 VDD + 0.3 0.8 VDDQ + 0.3 0.8 70 Unit V V V V V
C
Input
voltages1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. 2 VIL min. = -2.0V for pulse width less than 0.2 x tRC.
TQFP thermal resistance
Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1
1 This parameter is sampled.
Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51
Symbol
JA JC
Typical 46 2.8
Units
C/W C/W
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AS7C33128PFS32A AS7C33128PFS36A
(R)
DC electrical characteristics
-200 Parameter Input leakage current1 Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC2 ISB Standby power supply current ISB1 ISB2 Output voltage VOL VOH Test conditions VDD = Max, VIN = GND to VDD OE VIH, VDD = Max, VOUT = GND to VDD CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ VIL Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH IOL = 8 mA, VDDQ = 3.465V IOH = -4 mA, VDDQ = 3.135V -183 -166 -133 -100
Min Max Min Max Min Max Min Max Min Max Unit
- - - - - - - 2.4
2 2 570 160 30 30 0.4 -
- - - - - - - 2.4
2 2 540 140 30 30 0.4 -
- - - - - - - 2.4
2 2 475 130 30 30 0.4 -
- - - - - - - 2.4
2 2 425 100 30 30 0.4 -
- - - - - - - 2.4
2 2
A A
325 mA 90 30 30 0.4 - V mA
1 LBO pin has an internal pull-up and input leakage = 10 a. 2 ICC given with no output loading. ICC increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
-200 Parameter Output leakage current Output voltage Symbol |ILO| VOL VOH Test conditions OE VIH, VDD = Max, VOUT = GND to VDD IOL = 2 mA, VDDQ = 2.65V IOH = -2 mA, VDDQ = 2.35V -183 -166 -133 -100 Min Max Min Max Min Max Min Max Min Max Unit -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - -1 - 1.7 1 0.7 - A V
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Timing characteristics over operating range
-200 Parameter Clock frequency Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable LOW to data valid Clock HIGH to output Low Z Data output invalid from clock HIGH Output enable LOW to output Low Z Output enable HIGH to output High Z Clock HIGH to output High Z Output enable HIGH to invalid output Clock HIGH pulse width Clock LOW pulse width Address setup to clock HIGH Data setup to clock HIGH Write setup to clock HIGH Chip select setup to clock HIGH Address hold from clock HIGH Data hold from clock HIGH Write hold from clock HIGH Chip select hold from clock HIGH ADV setup to clock HIGH ADSP setup to clock HIGH ADSC setup to clock HIGH ADV hold from clock HIGH ADSP hold from clock HIGH ADSC hold from clock HIGH
1 See "Notes" on page 11.
-183
Min Max
-166
Min Max
-133
Min Max
-100
Min Max Unit Notes1
Sym fMax tCYC tCYCF tCD tCDF tOE tLZC tOH tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tADVS tADSPS tADSCS tADVH
Min
Max
- 5 9 - - - 0 1.5 0 - - 0 2.2 2.2 1.4 1.4 1.4 1.4 0.5 0.5 0.5 0.5 1.4 1.4 1.4 0.5
200 - - 3.0 8.5 3.0 - - - 3.0 3.0 - - - - - - - - - - - - - - - - -
- 5.4 10 - - - 0 1.5 0 - - 0 2.4 2.4 1.4 1.4 1.4 1.4 0.5 0.5 0.5 0.5 1.4 1.4 1.4 0.5 0.5 0.5
183 - - 3.1 9 3.1 - - - 3.1 3.1 - - - - - - - - - - - - - - - - -
- 6 10 - - - 0 1.5 0 - - 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5
166 - - 3.5 9 3.5 - - - 3.5 3.5 - - - - - - - - - - - - - - - - -
- 7.5 12 - - - 0 1.5 0 - - 0 2.5 2.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5
133 - - 4.0 10 4.0 - - - 4.0 4.0 - - - - - - - - - - - - - - - - -
- 10 12 - - - 0 1.5 0 - - 0 3.5 3.5 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 2.0 2.0 0.5 0.5 0.5
100 MHz - - 5.0 12 5.0 - - - 4.5 5.0 - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 2,3,4 2 2,3,4 2,3,4 2,3,4
tADSPH 0.5 tADSCH 0.5
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Key to switching waveforms
Rising input Falling input Undefined/don't care
Timing waveform of read cycle
tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS tAH Address A1 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 A2 A3 LOAD NEW ADDRESS tCYC tCL
CE1 tADVS tADVH ADV OE tHZOE tOH DOUT (pipelined mode) t OE tLZOE DOUT (flow-through mode) Q(A1)
Q(A2Y01)
tCD ADV INSERTS WAIT STATES tHZC
Q(A2Y01)
Q(A1)
Q(A2)
Q(A2Y10)
Q(A2Y11)
Q(A3)
Q(A3Y01)
Q(A3Y10)
Q(A2Y10)
Q(A2Y11)
Q(A3)
Q(A3Y01)
Q(A3Y10)
Q(A3Y11) tHZC
Note: Y = XOR when LBO= HIGH/No Connect; Y = ADD when LBO = LOW. BW[a:d] is don't care.
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Timing waveform of write cycle
tCYC tCH CLK tADSPS tADSPH ADSP tCL
tADSCS tADSCH ADSC
tAS tAH Address A1 A2
ADSC LOADS NEW ADDRESS A3
tWS BWE
BW[a:d]
tWH
tCSS tCSH CE0, CE2
CE1 ADV SUSPENDS BURST ADV tADVS tADVH
OE tDS tDH Data In
D(A1) D(A2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) D(A3) D(A3Y01) D(A3Y10)
Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW.
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AS7C33128PFS32A AS7C33128PFS36A
(R)
Timing waveform of read/write cycle
tCYC tCH CLK tADSPS tADSPH ADSP tAS tAH Address A1 A2 tWS tWH GWE A3 tCL
CE0, CE2
CE1 tADVS tADVH ADV
OE tDS tDH DIN tLZC tCD DOUT (pipeline mode) tCDF DOUT (flow-through mode) Q(A1)
Q(A3Y01) Q(A3Y10) Q(A3Y11)
D(A2) tHZOE tLZOE tOE Q(A3)
Q(A3Y01) Q(A3Y10) Q(A3Y11)
tOH
Q(A1)
Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW.
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(R)
AS7C33128PFS32A AS7C33128PFS36A
AC test conditions
* Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. * Input and output timing reference levels: 1.5V. +3.0V DOUT Z0 = 50 50 DOUT VL = 1.5V for 3.3V I/O; 353 / 1538 30 pF* = V DDQ/2 for 2.5V I/O Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319 / 1667 5 pF* GND *including scope and jig capacitance
90%
10% GND
90% 10%
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a:d]. 8 Chip select refers to CE0, CE1, CE2.
Package Dimensions 100-pin quad flat pack (TQFP)
TQFP Min
A1 A2 b c D E e Hd He L L1
Max
0.15 1.45 0.38 0.20 14.10 20.10
Hd D b
0.05 1.35 0.22 0.09 13.90 19.90
e
0.65 nominal 15.90 21.90 0.45 16.10 22.10 0.75
He E
1.00 nominal 0 7
Dimensions in millimeters
c L1 L A1 A2
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AS7C33128PFS32A AS7C33128PFS36A
(R)
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P. 12 of 13
(R)
AS7C33128PFS32A AS7C33128PFS36A
Ordering information
Package TQFP TQFP TQFP TQFP Width x32 x32 x36 x36 -200 MHz AS7C33128PFS32A200TQC AS7C33128PFS32A200TQI AS7C33128PFS36A200TQC AS7C33128PFS36A200TQI -183 MHz AS7C33128PFS32A183TQC AS7C33128PFS32A183TQI AS7C33128PFS36A183TQC AS7C33128PFS36A183TQI -166 MHz AS7C33128PFS32A166TQC AS7C33128PFS32A166TQI AS7C33128PFS36A166TQC AS7C33128PFS36A166TQI -133 MHz AS7C33128PFS32A133TQC AS7C33128PFS32A133TQI AS7C33128PFS36A133TQC AS7C33128PFS36A133TQI -100 MHz AS7C33128PFS32A100TQC AS7C33128PFS32A100TQI AS7C33128PFS36A100TQC AS7C33128PFS36A100TQI
Part numbering guide
AS7C 1 33 2 128 3 PF 4 S 5 32/36 6 A 7 -XXX 8 TQ 9 C/I 10
1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 128=128K 4.Pipeline-Flowthrough (each device works in both modes) 5.Deselect: S=Single cycle deselect 6.Organization: 32=x32; 36=x36 7.Production version: A=first production version 8.Clock speed (MHz) 9.Package type: TQ=TQFP 10.Operating temperature: C=Commercial (0 C to 70 C); I=Industrial (-40 C to 85 C)
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(c) Copyright A lliance Sem iconductor Corporation. All rights reserved. O ur three-point logo, our nam e and Intelliw att are tradem arks or registered tradem arks of Alliance. All other brand and product nam es m ay be the tradem arks of their respective com panies. A lliance reserves the right to m ake changes to this docum ent and its products at any tim e without notice. A lliance assum es no responsibility for any errors that m ay appear in this docum ent. T he data contained herein represents A lliance's best data and/or estim ates at the tim e of issuance. A lliance reserves the right to change or correct this data at any tim e, without notice. If the product described herein is under developm ent, significant changes to these specifications are possible. The inform ation in this product data sheet is intended to be general descriptive inform ation for potential custom ers and users, and is not intended to operate as, or provide, any guarantee or w arrantee to any user or custom er. A lliance does not assum e any responsibility or liability arising out of the application or use of any product described herein, and disclaim s any express or im plied warranties related to the sale and/or use of A lliance products including liability or warranties related to fitness for a particular purpose, m erchantability, or infringem ent of any intellectual property rights, except as express agreed to in A lliance's Term s and Conditions of Sale (w hich are available from A lliance). A ll sales of A lliance products are m ade exclusively according to Alliance's Term s and Conditions of Sale. T he purchase of products from A lliance does not convey a license under any patent rights, copyrights, m ask w orks rights, tradem arks, or any other intellectual property rights of A lliance or third parties. A lliance does not authorize its products for use as critical com ponents in life-supporting system s where a m alfunction or failure m ay reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting system s im plies that the m anufacturer assum es all risk of such use and agrees to indem nify A lliance against all claim s arising from such use.

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